Signal and Power Integrity
Can we tell you if your product will pass an EMI/EMC scan? Unfortunately not. However, weaknesses in a design can be highlighted and addressed using a ‘simulated’ pre-compliance scan.
Power-aware Signal Integrity Analysis
Signal integrity (SI) analysis allows visibility of how signals are going to behave as they traverse PCB traces, vias, connectors, passive components, etc. Power integrity (PI) analysis studies a design’s power delivery networks to evaluate power plane impedance, decoupling capacitance, etc. Analysis tools have historically treated these two issues separately, that is, signal integrity has assumed near perfect power supply and power integrity has not properly factored the impact of the switching signals. The two are inextricably linked and should be simulated simultaneously to avoid over-optimistic results.
The waveform below demonstrates the issue. The ideal VDDQ power supply is shown in red. The signal exhibits classic signal integrity artefacts, most noticeably overshoot and ringing as the signal settles. There is a small amount of noise on the static signal level caused by the switching of other signals in the memory interface (crosstalk).
Compare the above to the waveform to that below. The switching signals now cause perturbations in the VDDQ power supply (through the power/ground structure within the ICs). Crucially, this noise is impressed upon the signals that the voltage rail supplies with current.
Resonance analysis detects frequencies at which standing waves occur and the power supply structure resonates. This analysis takes into account all copper features, PCB stack-up and passive component models (e.g. bulk/decoupling capacitors).
Network Parameter Extraction
Network parameters can be extracted from any pins, nodes, ports, etc. Extracting the network behaviour between these nodes has many uses. Data can be exported as S-Parameter (Touchstone) format, it can be transformed into the Z domain to display power supply impedance profiles and it may be used to represent the circuit board in system-level simulations of DDR interfaces, SERDES channels, etc.
Channel analysis is a methodology that allows millions of bit transitions to be simulated in a multi-gigabit SERDES channel, allowing the channel’s bit error rate (BER) and data eye to be quantified. IBIS-AMI models from vendors including Xilinx, Altera and Intel allow channels to be simulated using accurate behavioural descriptions of the SERDES transceivers being employed. Optimum TX/RX settings may be found by exploring gain, emphasis and equalisation settings deep within the SERDES block.
DC Power Analysis
IC core power supplies continue to demand higher currents, placing greater demands on printed circuit power structures. Power analysis allows modelling of these DC interconnections, highlighting excessive current densities, hot-spots and IR-drop. Power delivery networks can quickly be evaluated to ensure sufficient via barrels, copper cross-sections, etc. exist to carry the required current and without losing too much power in the PCB as heat (a serious consideration on battery-life critical hardware).
Power delivery networks (PDNs) can involve extremely complicated PCB layout in order to connect the power supply to the power and ground pins of ICs. The electrical behaviour of the PDN will be affected by many things, including vias, traces, plane shapes, voids, inter-plane capacitance, capacitor types/values, capacitor mounting parasitics and PCB stack-up.
Impedance profiles are extracted from the printed circuit design to measure the performance of the power delivery networks. This view allows us to ‘look into’ the power planes from the ICs’ perspective and gauge whether or not the design is suitable for operation.