Technology & Examples

DDR3 Problem Statement

A client brought a new design to us that included an embedded chip-down DDR3 memory controller. During hardware bring-up the memory accesses were found to be unreliable, error-free on some days but barely operational on others. Performance seemed to be very dependant upon temperature and although down-clocking helped, it did not cure. This scenario is not uncommon with PCBs that were designed 'to rule'. Some effort had been made to keep signal paths consistent but no simulations had been run to verify the final layout. 





DDR3 Data Eye

DDR3 Power



The board was taken through our standard signal integrity analysis flow. Simulations were run to establish whether or not SI or PI (or both) were likely causes of poor performance. They were.The simulations took into account signal crosstalk, stack-up/materials, power supply noise, jitter, decoupling, power plane integrity, device packages...When all these factors were taken into consideration the tools provided a set of results that did not meet the JEDEC DDR3 specification (plots above). The DDR3 was re-routed using high-speed design constraints for the signal traces and power delivery networks. The simulations were repeated at the end of the design phase to verify the new layout. The design was found to now meet the DDR3 specifications and the client committed to manufacture. 

Through PVT testing, the resulting hardware was found to function correctly at full speed and with good headroom across variations in process, voltage and temperature.




DDR3 Data

When using simulation tools and techniques, an understandable concern for many design engineers is that the results will not be representative of what would be seen in the real world. Simulation results need to be accurate enough to correctly guide the decisions being made through the design process, but they do not necessarily need to be 100% true to real world measurement. 

What IS important though is that there is a sufficient level of accuracy among all the elements in a simulated topology. Connectors, traces, vias, cables, etc. all need a suitably accurate model for us to have faith in the results. For example, there is little point simulating a SERDES channel at great accuracy if key component models, such as connectors, are missing from the topology. 

That said, when all elements are in place it is our experience that simulation results DO correlate well with real world measurement. Due to demand, the quality and availability of simulation models has improved year on year. Component vendors recognise that simulation is a vital part of product design and that failure to provide modelling information will ultimately result in lost sales.

To illustrate correlation between ADS simulations and real world measurement, study the images below. The oscilloscope waveforms show the transmitter (top left) and receiver (bottom left) eye diagrams of a 5Gbps PCI-Express channel, captured using an Agilent oscilloscope. The ADS waveforms show the simulated transmitter (top right) and receiver (bottom right) eye diagrams as seen in the Advanced Design System ‘FrontPanel’ eye tool. The channel being examined spans three printed circuit boards, traverses two high-speed backplane connectors and includes multiple signal vias and through-holes.


As can be clearly seen, there is very strong correlation between the simulated and measured results. Adjusting pre-emphasis and drive strengths settings in the transmitter was found to give almost identical receiver performance in both simulations and real-world measurement and receiver (bottom left) eye diagrams of a 5Gbps PCI-Express channel, captured using an Agilent oscilloscope. The ADS waveforms show the simulated transmitter (top right) and receiver (bottom right) eye diagrams as seen in the Advanced Design System ‘FrontPanel’ eye tool. The channel being examined spans three printed circuit boards, traverses two high-speed backplane connectors and includes multiple signal vias and through-holes. As can be clearly seen, there is very strong correlation between the simulated and measured results. Adjusting pre-emphasis and drive strengths settings in the transmitter was found to give almost identical receiver performance in both simulations and real-world measurement.

Fibreglass Weave Effect - should I be concerned?

There has been much talk in recent years about 'fibreglass weave effect' in relation to differential signal routing. We are frequently being asked whether or not this is a genuine problem that needs addressing in PCB layouts, or just a statistical possibilty. If you are not aware of this issue or its effect on multi-gigabit serial links, here is a brief explanation...


Traditional printed circuit boards use laminations of fibreglass composite and copper foil. The fibreglass composite consists of woven glass yarns encapsulated in a resin matrix, usually a form of epoxy resin. Generally, ‘bulk’ electrical data is given for the composite material as a whole (e.g. a dielectric constant of 4.1 @ 1GHz) and this approach has sufficed for many years, allowing designers to calculate the characteristic impedance, propagation velocity, etc. for signal conductors.

High-speed signalling in the multi-gigahertz regime uses differential signal transmission. Differential signals use a true (P) and a complement (N) signal, one being an inversion of the other. This technology offers great immunity from common-mode noise, and yields excellent signal integrity provided that uniform impedance is achieved and that the pair of signals arrive at the receiver simultaneously. Any difference in signal arrival time between the P and the N signal will reduce the signal's 'eye aperture' and limit the maximum rate at which data can be successfully transmitted. Constantly increasing data rates have led to very stringent matching requirements between the legs of the differential pair. This is addressed in the PCB layout by making the two conductors exactly the same length.

What’s the Problem?

EDA/CAD tools are now loaded with features to help achieve these goals. Accurate delay matching between the P and N signals is achieved through ‘Delay Tuning’ and ‘Differential Phase’ utilities and design rules. However, these utilities assume bulk electrical figures and cannot take into account variations in the final laminate. The fibreglass weaving process results in yarns of glass that are perpendicular to one another. By default, traces will tend to traverse a PCB at 0°, 45° or 90° and differential signal traces will therefore tend to follow the bundles of glass yarn within the laminate. The reason this is significant is that the glass and resin actually have very different dielectric properties. Glass is typically much higher than the quoted bulk figure, ~6 and resin is typically much lower, ~3. For certain woven glass styles (e.g. ‘106’ and ‘1080’) there exists a loose weave pattern with a high resin-content. A differential pair that uses a trace pitch of around half the weave pitch could quite feasibly see a much lower dielectric constant on one conductor than the other. This property affects propagation delay and therefore all the effort that has been spent closely matching these traces in the design could be undone by the material itself.


The image below shows a weave of glass yarns in relation to the routing of two differential pairs. In the upper pair the red signal will see a lower εr value than the blue signal. This is because the red trace is aligned with the resin-rich gaps in the glass weave, whereas the blue trace is aligned with the glass bundle. In the lower pair the opposite is true and the blue signal will see a lower εr value than the red signal. This will cause a difference in propagation velocity between the two elements within each pair.


Glass Weave in Dielectric and two Differential Pairs


Glass Weave


How Significant is the Effect?

It could be very significant. Much of the literature in circulation demonstrates 'weave effect' at very high data-rates and extreme trace lengths. This might cause many to believe that the problem only applies to the biggest and fastest of designs. Indeed, the effects will be felt worst in these designs, but mismatch in delay between P and N will erode margin in any design. Below are some simulations using a more common trace length and data rate. In these simulations the dielectric constant is varied to give a mismatch between the P and N signals.


Eye Diagrams: Dielectric constant =4.5 versus dielectric constant of 4.2 (P) & 4.8 (N)


Eye Diagram dK=4.5 Eye Diagram dK=4.2 and 4.8

Trace length: 300mm, Data rate: 5Gbps, 100,000 bits including jitter.


What Can be Done?

There are various things that can be done to avoid the deterimental affects of glass weave, but each comes at a price and not all will suit a particular design. Here are some of them...


Rotate the design in the manufacturing panel. This apparently simple process will remove parallelism between signal traces and glass fibre yarns.


Pros: Little additional design effort.

Cons: Experience is showing this to be very expensive. A large amount of material is wasted and this will be reflected in the cost of the boards. If the rotation causes the manufacture to go from ‘2 per panel’ to ‘1 per panel’ (for example) then expect the cost to increase dramatically. Furthermore, for physically large designs this may not be possible.


Use homogenous materials. This will remove woven materials entirely and remove any local variation in dielectric constant.


Pros: Little additional design effort.

Cons: Very expensive, exotic materials. Lead time problems, limited fabricators able to processes. 


Use modified fibreglass. Some products, e.g. Novaspeed, use modified glass with a dielectric constant closer to that of the resin matrix. This drastically reduces effects caused by the fibre weave.


Pros: Little additional design effort.

Cons: Expensive, single-source materials. Lead time problems. 


Use trace widths and spacings that are large enough to offer immunity to the local variation in dielectric properties due to weave pattern.


Pros: Little additional design effort.

Cons: These are almost certainly 85R to 100R differential impedance signals and to get traces sufficiently wide would require very thick dielectrics. It is likely that this is not possible to achieve on a fixed thickness board.


Avoid using '104', '106', '1065' and '1080' style glass cloths. Specify only dense weave styles, e.g. from '2112' onwards. 


Pros: Standard materials can be used, no additional cost in manufacture, no additional leadtime concerns. Only additional effort is in managing stack-up design and ensuring this is used in procurement.

Cons: The materials that we want to avoid are exactly the materials that the PCB suppliers love using! The loose weave makes the materials resin-rich. To fabricate a solid laminate with no voids, resin-rich materials are ideal. They allow fine metal features and small gaps to be used in the PCB without the risk of resin starvation. Specifying only dense weave materials may lead to a laminate that is unmanufacturable, or has poor mechanical integrity.  


Design all high-speed differential traces to be at an angle to the weave pattern.


Pros: Standard materials can be used, no additional cost in manufacture, no additional leadtime concerns.

Cons: Requires extra design effort in the layout phase. Modifying the design on a re-spin can require additional time.  



There is no doubt that the fibreglass weave can affect performance once data rates reach a few gigabits per second. Intel has carried out tests on large batches of boards and has found the phenomena to be real and demonstrable. The effect will be seen least in short traces and in traces that run at arbitrary angles to the weave direction. Weave effect is a statistical problem. It may be the case that no issue is ever seen during the design phase, but as the number of units produced increases so too does the probability that the problem will arrise. Of all the ways of avoiding the problem, the most cost effective and reliable way would seem to be to eliminate the problem 'by design', avoiding long trace runs at 0 and 90 degrees. Several of our clients now request that their differential signals are routed at an angle to the weave direction. We expect many more to follow...


PCI-Express Problem Statement 

A client experienced excessive bit errors on a 5Gbps (Gen2) PCI-Express link. The link includes multiple vias, connectors, backplane, long traces, etc. The objective is to find the cause of this high BER (bit error rate) and identify ways to reduce it.






The link was modelled in our simulation tools. The topology includes s-parameter models of connectors, traces and vias, component breakout regions (BORs), series capacitors and SERDES driver/receiver. Simulations were run, using hundreds of thousands of bit transitions to characterise the link.





The analysis provided a list of changes that could be made to the design and, more importantly, the amount of benefit that would be gained from each change. This allowed the client to address the simple changes that would give a significant improvement in performance, without being distracted by difficult ‘tweaks’ that give no real benefit.

The ‘design-space’ was explored to find what improvements could be made to improve the eye diagram / BER.




At gigabit data rates ‘the Devil is in the detail’. The smallest conductor features can have a measurable (and detrimental) effect upon signal quality. Consider the differential vias shown below. These vias have an identical structure, except for the internal layer on which the traces are routed.

The signal in the left-hand image traverses the shortest length of via but experiences a ‘stub’ of via barrel that will resonate at frequencies relating to its physical length.


Conversely, the via on the right traverses the majority of the via barrel but benefits from minimal stub length. These via features were simulated in order to create a set of via models for use in further ‘channel simulations’.

The inset graphs are for S21 (insertion loss) against frequency and show a stark amount of difference in the GHz regime. A clear resonance is seen in the case of the via stub.


This methodology is used extensively to create S-Parameter models of vias, through-holes, BGA breakout regions (BORs) and RF antenna artworks.


Since its introduction in 1993, the I/O Buffer Information Specification (IBIS) has allowed IC vendors to publish the IO characteristics of their silicon without disclosing their confidential IP. Whilst these behavioural models have allowed engineers to properly design PCB layouts and termination schemes, a question mark has always hung over the issue of very high-speed signalling. Due to the complexity of SERDES transceivers, vendors have typically released encrypted HSPICE models for MGbit IOs, rather than use IBIS. Unfortunately, using transistor-level models for designing a MGbit link is a practical impossibility. To properly characterise a MGbit link requires millions of bit transitions to be performed which would take a vast  amount of time in transient analysis. To design a link requires many different configurations to be tested and, once a few variables are included in the simulation, the 'exploration space' becomes too big.


IBIS version 5.0 resolves this problem by using a new standard called IBIS-AMI (Algorithmic Modelling Interface). Using this methodology, MGbit channels can be characterised extremely quickly and with accurate results that correlate well with real world measurement.   


Benefits of AMI

Key benefits of IBIS-AMI are:

  • Fast simulations, with huge data throughput
  • Ability to program CDR, equalisation, etc.
  • Interoperability between IC vendors
  • Model availability from key SERDES vendors (notably Xilinx and Altera) 

For more information on IBIS-AMI simulations, please contact us.